University Study Materials 4 U

ME CSE Syllabus-regulation 2013   ME CSE Syllabus-regulation 2009

An interrupt that occurs when a program requests data that is not currently in real memory. The interrupt triggers the operating system to fetch the data from a virtual memory and load it into RAM. An invalid page fault or page fault error occurs when the operating system cannot find the data in virtual memory. This usually happens when the virtual memory area, or the table that maps virtual addresses to real addresses, becomes corrupt. A page fault is a trap to the software raised by the hardware when a program accesses a page that is mapped in the virtual address space, but not loaded in physical memory. The hardware that detects a page fault is the memory management unit in a processor. The exception handling software that handles the page fault is generally part of the operating system. Types of Page Faults 1. Minor If the page is loaded in memory at the time the fault is generated, but is not marked in the memory management unit as being loaded in memory, then it is

A page is a sequence of N bytes where N is a power of 2. Let's assume that we have 1M of RAM. RAM is also called physical memory. We can subdivide the RAM into 4K pages. Thus 1M / 4K = 256 pages.  Thus, our RAM has 256 physical pages, each holding 4K. Fig 1: Address translation from virtual to physical Page Table How is an address translated from virtual to physical? Fig 2: Page Table First, like the cache, we split up a 32 bit virtual address into a virtual page (which is like a tag) and a page offset. We must convert the virtual page number to a physical page number. For example, The virtual page consists of 20 bits.  A page table is a data structure which consists of 2 20 page table entries (PTEs).  The page table as an array of page table entries, indexed by the virtual page number. The page table's index starts at 0, and ends at 2 20 - 1. Suppose your program generates a virtual address. You'd extract bits B 31-12 to get the virtual p

If you think it’s there, and it’s there…it’s real. If you think it’s not there, and it’s there…it’s transparent. If you think it’s there, and it’s not there…it’s imaginary. If you think it’s not there, and it’s not there…it’s nonexistent. Virtual memory is imaginary memory: it gives you the illusion of a memory arrangement that’s not physically there. If your computer lacks the random access memory (RAM) needed to run a program or operation, Windows uses virtual memory to compensate. Virtual memory combines your computer’s RAM with temporary space on your hard disk.  When RAM runs low, virtual memory moves data from RAM to a space called a paging file .  Moving data to and from the paging file frees up RAM to complete its work. You can think of virtual memory as an alternate set of memory addresses. Programs use these virtual addresses rather than real addresses to store instructions and data. When the program is actually executed, the virtual addresses are c

A multilevel cache hierarchy consists of n levels of caches. C1, C2, .......,Ci,....... Cn. A processor reference is serviced by the cache closest to the processor that contains the data.  At the same time that cache provides information to the caches on the path between itself and the processor. Multilevel cache hierarchy for multi- processors neither a local LRU nor a global LRU. Where all references to a Ci cache are percolated to its parent for rear-ranging the LRU stack at the Ci+i level. Multilevel caches Another issue is the fundamental tradeoff between cache latency and hit rate.  Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches. Multi-level caches generally operate by checking the smallest level 1 (L1) cache first. If it hits, the processor proceeds at high speed.  If the smaller cache misses, the next larger cache (L2) is c

Cache memory Operations in Cache Memory Multilevel Cache Memory